"A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS ..."

Chiou-Bang Chen, Horng-Yuan Shih (2010)

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DOI: 10.1109/ICECS.2010.5724452

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Chiou-Bang Chen, Horng-Yuan Shih:
A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process. ICECS 2010: 53-56

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