"Hardware Implementation of Floating Point Matrix Inversion Modules on FPGAs."

S. Chetan et al. (2020)

> Home

Details and statistics

DOI: 10.1109/ICM50269.2020.9331796

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icm2/ChetanMLS20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icm2/ChetanMLS20
S. Chetan, J. Manikandan, V. Lekshmi, S. Sudhakar:
Hardware Implementation of Floating Point Matrix Inversion Modules on FPGAs. ICM 2020: 1-4

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.