"Concurrent logic and interconnect delay estimation of MOS circuits by ..."

Sambuddha Bhattacharya, Chuanjin Richard Shi (2003)

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DOI: 10.1109/ISCAS.2003.1206183

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-29

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Sambuddha Bhattacharya, Chuanjin Richard Shi:
Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. ISCAS (4) 2003: 660-663

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