"Dual clock rate block data parallel architecture."

An-Te Deng, Winser E. Alexander (2003)

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DOI: 10.1109/ISCAS.2003.1205996

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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An-Te Deng, Winser E. Alexander:
Dual clock rate block data parallel architecture. ISCAS (4) 2003: 532-535

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