"Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area ..."

Ginés Doménech-Asensi et al. (2025)

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DOI: 10.1109/ISCAS56072.2025.11043424

access: closed

type: Conference or Workshop Paper

metadata version: 2025-07-08

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Ginés Doménech-Asensi, Francisco Javier Andreo-Oliver, Ramón Ruiz Merino, José Ángel Díaz-Madrid:
Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. ISCAS 2025: 1-5

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