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"Hardware reduction using a 6-connectivity interconnection network over a ..."

Valentin Gies, Thierry M. Bernard, Alain Mérigot (2005)

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DOI: 10.1109/ISCAS.2005.1465065

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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Valentin Gies, Thierry M. Bernard, Alain Mérigot:
Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor. ISCAS (3) 2005: 2227-2230

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