"A routability and performance driven technology mapping algorithm for LUT ..."

Chi-Chou Kao, Yen-Tai Lai (1999)

> Home

Details and statistics

DOI: 10.1109/ISCAS.1999.777928

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/KaoL99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/KaoL99
Chi-Chou Kao, Yen-Tai Lai:
A routability and performance driven technology mapping algorithm for LUT based FPGA designs. ISCAS (1) 1999: 474-477

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.