"Fast and memory efficient VLSI architecture for output probability ..."

Kazuhiro Nakamura et al. (2008)

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DOI: 10.1109/ISCAS.2008.4541761

access: closed

type: Conference or Workshop Paper

metadata version: 2020-12-29

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Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi:
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems. ISCAS 2008: 1688-1691

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