"Synthesis of partition-codec architecture for low power and small area ..."

Shanq-Jang Ruan et al. (2001)

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DOI: 10.1109/ISCAS.2001.922100

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-09

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Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai:
Synthesis of partition-codec architecture for low power and small area circuit design. ISCAS (5) 2001: 523-526

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