"A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path ..."

Zhongkai Wang et al. (2024)

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DOI: 10.1109/ISCAS58744.2024.10558449

access: closed

type: Conference or Workshop Paper

metadata version: 2025-05-26

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Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. ISCAS 2024: 1-5

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