"Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V ..."

Andreas Wassatsch, Dirk Timmermann (2001)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2001.922178

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/WassatschT01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/WassatschT01
Andreas Wassatsch, Dirk Timmermann:
Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. ISCAS (4) 2001: 92-95

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.