"A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process."

R. Rajendran, P. V. Ramakrishna (2012)

> Home

Details and statistics

DOI: 10.1109/ISED.2012.63

access: closed

type: Conference or Workshop Paper

metadata version: 2019-02-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ised/RajendranR12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ised/RajendranR12
R. Rajendran, P. V. Ramakrishna:
A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process. ISED 2012: 23-27

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.