"Novel STT-MRAM-based last level caches for high performance processors ..."

Shinobu Fujita et al. (2014)

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DOI: 10.1109/ISICIR.2014.7029504

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-19

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Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe:
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC 2014: 316-319

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