"Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a ..."

Shintaro Harada et al. (2014)

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DOI: 10.1109/ISMVL.2014.45

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka:
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. ISMVL 2014: 214-219

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