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"Physical-aware system-level design for tiled hierarchical chip ..."

Jordi Cortadella et al. (2013)

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DOI: 10.1145/2451916.2451920

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-14

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  dblp key:
  - conf/ispd/CortadellaPNP13
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  - https://dblp.org/rec/conf/ispd/CortadellaPNP13
Jordi Cortadella, Javier de San Pedro, Nikita Nikitin, Jordi Petit:
Physical-aware system-level design for tiled hierarchical chip multiprocessors. ISPD 2013: 3-10

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