"Transaction Level Error Susceptibility Model for Bus Based SoC Architectures."

Ing-Chao Lin et al. (2006)

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DOI: 10.1109/ISQED.2006.138

access: closed

type: Conference or Workshop Paper

metadata version: 2025-10-14

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Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada:
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. ISQED 2006: 775-780

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