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"Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double ..."

Saibal Mukhopadhyay et al. (2005)

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DOI: 10.1109/ISQED.2005.77

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
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  - https://dblp.org/rec/conf/isqed/MukhopadhyayKKLJCR05
Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415

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