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ORCID"Power & variability test chip architecture and 45nm-generation ..."
R. Venkatraman et al. (2009)
- R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh:
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. ISQED 2009: 27-32
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