"Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for ..."

Kumar Yelamarthi, Chien-In Henry Chen (2007)

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DOI: 10.1109/ISQED.2007.162

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Kumar Yelamarthi, Chien-In Henry Chen:
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. ISQED 2007: 426-431

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