"A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline ..."

James Bailey et al. (2021)

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DOI: 10.1109/ISSCC42613.2021.9365853

access: closed

type: Conference or Workshop Paper

metadata version: 2022-03-23

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James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan:
A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. ISSCC 2021: 140-142

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