"A power-efficient 32b ARM ISA processor using timing-error detection and ..."

David M. Bull et al. (2010)

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DOI: 10.1109/ISSCC.2010.5433919

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type: Conference or Workshop Paper

metadata version: 2018-07-31

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David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. ISSCC 2010: 284-285

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