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"A fractional-N digital PLL with background-dither-noise-cancellation loop ..."

Cheng-Ru Ho, Mike Shuo-Wei Chen (2018)

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DOI: 10.1109/ISSCC.2018.8310350

access: closed

type: Conference or Workshop Paper

metadata version: 2018-03-14

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Cheng-Ru Ho, Mike Shuo-Wei Chen:
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ISSCC 2018: 394-396

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