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"2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL ..."

Zhiqiang Huang et al. (2016)

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DOI: 10.1109/ISSCC.2016.7417896

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-15

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Zhiqiang Huang, Bingwei Jiang, Lianming Li, Howard Cam Luong:
2.3 A 4.2µs-settling-time 3rd-order 2.1GHz phase-noise-rejection PLL using a cascaded time-amplified clock-skew sub-sampling DLL. ISSCC 2016: 40-41

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