"8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ ..."

James Myers et al. (2015)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2015.7062967

access: closed

type: Conference or Workshop Paper

metadata version: 2022-01-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/MyersSHGPF15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/MyersSHGPF15
James Myers, Anand Savanth, David Howard, Rohan Gaddh, Pranay Prabhat, David Flynn:
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications. ISSCC 2015: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.