"A 65nm Single-Chip Application and Dual-Mode Baseband Processor with ..."

Masao Naruse et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523156

access: closed

type: Conference or Workshop Paper

metadata version: 2019-02-19

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Masao Naruse, Tatsuya Kamei, Toshihiro Hattori, Takahiro Irita, Kenichi Nitta, Takao Koike, Shinichi Yoshioka, Koji Ohno, Masahito Saigusa, Minoru Sakata, Yukio Kodama, Yuji Arai, Teruyoshi Komuro:
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU. ISSCC 2008: 260-261

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