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"7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization ..."

Hiroki Noguchi et al. (2016)

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DOI: 10.1109/ISSCC.2016.7417942

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-22

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  - conf/isscc/NoguchiITAKKHAS16
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  - https://dblp.org/rec/conf/isscc/NoguchiITAKKHAS16
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC 2016: 132-133

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