"A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no ..."

Tae-Young Oh et al. (2010)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2010.5433889

access: closed

type: Conference or Workshop Paper

metadata version: 2021-06-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/OhSBPLCKKKKKKKKKLLSYCBYCMPHLPCJ10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/OhSBPLCKKKKKKKKKLLSYCBYCMPHLPCJ10
Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun:
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. ISSCC 2010: 434-435

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.