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"A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 ..."

Bharath Raghavan et al. (2013)

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DOI: 10.1109/ISSCC.2013.6487624

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-21

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  - conf/isscc/RaghavanCSMPVHMC13
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  - https://dblp.org/rec/conf/isscc/RaghavanCSMPVHMC13
Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. ISSCC 2013: 32-33

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