BibTeX record conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09

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@inproceedings{DBLP:conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09,
  author    = {Hidehiro Shiga and
               Daisaburo Takashima and
               Shinichiro Shiratake and
               Katsuhiko Hoya and
               Tadashi Miyakawa and
               Ryu Ogiwara and
               Ryo Fukuda and
               Ryosuke Takizawa and
               Kosuke Hatsuda and
               Fumiyoshi Matsuoka and
               Yasushi Nagadomi and
               Daisuke Hashimoto and
               Hisaaki Nishimura and
               Takeshi Hioka and
               Sumiko M. Doumae and
               Shoichi Shimizu and
               Mitsumo Kawano and
               Toyoki Taguchi and
               Yohji Watanabe and
               Shuso Fujii and
               Tohru Ozaki and
               Hiroyuki Kanaya and
               Yoshinori Kumura and
               Yoshiro Shimojo and
               Yuki Yamada and
               Yoshihiro Minami and
               Susumu Shuto and
               Koji Yamakawa and
               Soichi Yamazaki and
               Iwao Kunishima and
               Takeshi Hamamoto and
               Akihiro Nitayama and
               Tohru Furuyama},
  title     = {A 1.6GB/s {DDR2} 128Mb chain FeRAM with scalable octal bitline and
               sensing schemes},
  booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
               Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
               2009},
  pages     = {464--465},
  publisher = {{IEEE}},
  year      = {2009},
  url       = {https://doi.org/10.1109/ISSCC.2009.4977509},
  doi       = {10.1109/ISSCC.2009.4977509},
  timestamp = {Fri, 15 Jan 2021 14:20:21 +0100},
  biburl    = {https://dblp.org/rec/conf/isscc/ShigaTSHMOFTHMNHNHDSKTWFOKKSYMSYYKHNF09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}