"A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with ..."

Kyomin Sohn et al. (2008)

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DOI: 10.1109/ISSCC.2008.4523219

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Kyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim:
A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. ISSCC 2008: 386-387

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