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"A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with ..."

Chen Kong Teh et al. (2011)

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DOI: 10.1109/ISSCC.2011.5746344

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada:
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. ISSCC 2011: 338-340

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