"Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed ..."

Peter Celinski et al. (2004)

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DOI: 10.1109/ISVLSI.2004.1339519

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis:
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. ISVLSI 2004: 127-134

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