"Statistical Gate Sizing for Yield Enhancement at Post Layout Level."

Narender Hanchate, Nagarajan Ranganathan (2007)

Details and statistics

DOI: 10.1109/ISVLSI.2007.92

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.