"Reducing the Communication Bottleneck via On-Chip Cosimulation of ..."

Alexander Maili et al. (2005)

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DOI: 10.1109/ISVLSI.2005.61

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Alexander Maili, Christian Steger, Reinhold Weiss, Rob Quigley, Damian Dalton:
Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator. ISVLSI 2005: 290-291

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