"A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO ..."

Patroklos Pazionis et al. (2025)

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DOI: 10.1109/ISVLSI65124.2025.11130203

access: closed

type: Conference or Workshop Paper

metadata version: 2025-09-02

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Patroklos Pazionis, Andreas Tsimpos, Gerasimos Theodoratos, Georgios Panagopoulos:
A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration. ISVLSI 2025: 1-6

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