"Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal ..."

K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas (2007)

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DOI: 10.1109/ISVLSI.2007.35

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas:
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. ISVLSI 2007: 401-408

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