"Scalable and Power-Efficient Merging Network Design: Automatic RTL ..."

Ardhendu Sarkar, Sriparna Mandal, Surajeet Ghosh (2025)

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DOI: 10.1109/ISVLSI65124.2025.11130285

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type: Conference or Workshop Paper

metadata version: 2025-10-14

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Ardhendu Sarkar, Sriparna Mandal, Surajeet Ghosh:
Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGA. ISVLSI 2025: 1-6

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