"Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology."

A. S. Seyedi et al. (2006)

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DOI: 10.1109/ISVLSI.2006.28

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha:
Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. ISVLSI 2006: 373-377

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