"Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic."

Robert Wille et al. (2012)

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DOI: 10.1109/ISVLSI.2012.43

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/isvlsi/WilleSSD12
Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler:
Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI 2012: 213-218

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