"Architecture Exploration and Delay Minimization Synthesis for SET-Based ..."

Chia-Cheng Wu et al. (2018)

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DOI: 10.1109/ISVLSI.2018.00055

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang:
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. ISVLSI 2018: 257-262

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