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"Timing with Virtual Signal Synchronization for Circuit Performance and ..."

Grace Li Zhang, Bing Li, Ulf Schlichtmann (2018)

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DOI: 10.1109/ISVLSI.2018.00135

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-12

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  dblp key:
  - conf/isvlsi/Zhang0S18
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  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/Zhang0S18
Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. ISVLSI 2018: 715-718

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