"Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design."

Zhou Zhao et al. (2017)

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DOI: 10.1109/ISVLSI.2017.104

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/isvlsi/ZhaoCSPM17
Zhou Zhao, Xinlu Chen, Ashok Srivastava, Lu Peng, Saraju P. Mohanty:
Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design. ISVLSI 2017: 562-567

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