"Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing."

Ramyanshu Datta et al. (2004)

Details and statistics

DOI: 10.1109/TEST.2004.1387386

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.