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"A Method to Generate Tests for Combinational Logic Circuits Using an ..."

Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato (1988)

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DOI: 10.1109/TEST.1988.207786

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato:
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. ITC 1988: 102-107

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