"Optimal placement of IEEE 1149.1 test port and boundary scan resources for ..."

David L. Landis, Padmaraj Singh (1990)

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DOI: 10.1109/TEST.1990.114009

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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David L. Landis, Padmaraj Singh:
Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration. ITC 1990: 120-126

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