"DART: Dependable VLSI test architecture and its implementation."

Yasuo Sato et al. (2012)

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DOI: 10.1109/TEST.2012.6401581

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/itc/SatoKYHIMUHSS12
Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10

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