"Clock control architecture and ATPG for reducing pattern count in SoC ..."

Tom Waayers et al. (2010)

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DOI: 10.1109/TEST.2010.5699211

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab:
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC 2010: 114-123

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