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"Improving a design methodology of synthesizable VHDL with formal verification."

Luis Gustavo Perpetuo Costa Marques, Max Hering de Queiroz, Jean-Marie Farines (2016)

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DOI: 10.1109/LASCAS.2016.7451007

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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  dblp key:
  - conf/lascas/MarquesQF16
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  - https://dblp.org/rec/conf/lascas/MarquesQF16
Luis Gustavo Perpetuo Costa Marques, Max Hering de Queiroz, Jean-Marie Farines:
Improving a design methodology of synthesizable VHDL with formal verification. LASCAS 2016: 51-54

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