"A Stacked FPGA utilizing 3D-SRAM with Latency Optimization."

Ryo Takahashi, Kota Ando, Hiroki Nakahara (2024)

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DOI: 10.1109/MCSOC64144.2024.00072

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-21

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Ryo Takahashi, Kota Ando, Hiroki Nakahara:
A Stacked FPGA utilizing 3D-SRAM with Latency Optimization. MCSoC 2024: 400-406

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