"A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 ..."

Mari Yasunaga et al. (2023)

> Home

Details and statistics

DOI: 10.1109/MCSOC60832.2023.00077

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/mcsoc/YasunagaSWKCYM23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/mcsoc/YasunagaSWKCYM23
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura:
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC 2023: 478-485

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.